ZYNQ PS GPIO MIO 基础知识 - CSDN博客
2020年10月12日 · mio是zynq芯片ps端的基础外设io，可以连接诸如spi，i2c，uart，gpio等，通过vivado软件设置，软件可以将信号通过mio导出，同样也可以将信号通过emio（后续试验会介绍emio）连接到pl端的引脚上。
ZYNQ PS端MIO的使用——FPGA Vitis篇 - CSDN博客
mio是zynq芯片ps端的基础外设io，可以连接诸如spi，i2c，uart，gpio等，通过vivado软件设置，软件可以将信号通过mio导出，同样也可以将信号通过emio（后续试验会介绍emio）连接到pl端的引脚上。
ZYNQ7000-MIO与EMIO详解 - CSDN博客
2022年10月21日 · 总结一下，除去电源、地、时钟、复位、JTAG这五种引脚外，PS部分还有专门对接DDR，SRAM，USB的引脚，PL部分只有XADC和一些芯片的MGTX引脚是专用的，其余引脚均可任意配置。 1.2 电源引脚. PS与PL部分均需要多种电平的供电电源，电源需要从特定的电源引脚接入芯片。 相关电源引脚（包含ADC与地）信息如下表所示。 1.3 PS信号引脚. PS部分除电源引脚外的引脚信息如下图所示。 从这里可以看出来， PS部分的引脚除了电源、地、时钟、复 …
PL access to PS MIO pins - AMD
We can have PS periphs access MIO pins (top-left pic), or optionally go to the PL via EMIO (top-right). However, it's not clear to me if we can configure things such that the PL controls selective PS_MIO pins as in the bottom pic?
Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9
These mode pins share the multiuse I/O pins on the PS side of the device. In all, there are seven mode pins mapped to MIO[8:2]. The first four mode pins define the boot mode; the fifth determines whether the PLL is used or not; and the sixth and seventh mode pins define the bank voltages on MIO bank 0 and bank 1 during power up.
4、ZYNQ PS外设GPIO之MIO/EMIO - 孤情剑客 - 博客园
2022年7月10日 · mio 的 ps 外设的大多数 i/o 信号（ usb 除外）可以通过 mio 路由到 ps 引脚，或通过 emio 路由到 pl 引脚。 除千兆以太网外，大多数外设还在 MIO 和 EMIO 之间保持相同的协议。
MIO Pin List - adaptivesupport.amd.com
Where can I see the dedicated pin name of MIO pins? For ex: I want to check which is TX & RX pins of UART0 among the available MIO pins. My FPGA part no. is XCZU4EG-1SFVC784E.
Table MIO Interfaces - Xilinx Support
The new At-A-Glance table still does its intended function: it shows which MIO pins are used by an interface. The table is really only meant to give you an overview/idea as to which interfaces you can operate simultaneously, since interfaces span various MIO's and their MIO pin requirements can possibly conflict with each other.
̶ PS I/O pin assignments are typically the result of trade-offs between functions, as they are multiplexed onto the same bonded out I/O pins, known as MIO pins. ̶ The MIO pins are divided into two banks, i.e. Bank 0 = MIO0-15 and Bank 1 = MIO16-53. In Vivado the I/O voltage levels for both these banks are set to 3.3V (and not 1.8V).
Tom's computer pages
Everything you need to know is in the table on page 166 of the TRM. As it turns out, all you care about are 3 bits. These are the low 3 boot_modes bits, which are given on these pins: Boot_mode-2 == MIO-4 Boot_mode-1 == MIO-3 Boot_mode-0 == MIO-5. Who knows why it is in this crazy order, but it is.